1. Field of the Invention
The present invention is related to the field of write drivers used to operate inductive recording heads for magnetic recording.
2. Background Art
The present invention is a (HDD) two-terminal inductive head write driver having a head voltage that swings between the upper and lower supply voltage rails. A two-terminal inductive head write driver having a rail-to-rail head voltage swing is particularly useful for recording mechanisms (read/write) that are powered by lower supply voltage sources (i.e., 3.3 V). Because of this capability, a 3.3 V write driver maintains the same performance characteristics as magnetic recording devices that are powered at supply voltage levels of 5 V and 12 V.
FIG. 1 is a detailed diagram of a typical prior art circuit for implementing a write driver comprising four NPN transistors Q101-Q104, an inductive load, L.sub.HEAD, Schottky NPN transistors Q105-Q106, a bandgap voltage reference, V.sub.BG, and operational amplifier, OP1. A first transistor pair Q101 and Q102 are coupled in parallel having a common collector that is coupled to supply voltage, V.sub.CC. Inductive load, L.sub.HEAD, is coupled between the emitters of transistors Q101 and Q102. The emitters of transistors Q101 and Q102 are also coupled to the collectors of transistors Q103 and Q104, respectively. The second transistor pair Q103 and Q104 are coupled in parallel having a common emitter that is coupled to the first terminal of resistor R.sub.WC and the inverting input of operational amplifier OP1. The second terminal of resistor R.sub.WC is coupled to ground.
Bandgap voltage reference V.sub.BG is coupled between ground and the non-inverting input of operational amplifier OP1. The output of operational amplifier OP1 is coupled to the first terminals of resistors R103 and R104. The second terminal of resistor R103 is coupled to the anode of Schottky diode D101 and the base of Schottky transistor Q105. A first input voltage V.sub.DX is provided to the cathode of Schottky diode D101. Similarly, the second terminal of resistor R104 is coupled to the anode of Schottky diode D102 and the base of Schottky transistor Q106. Also, a second input voltage V.sub.DY is provided to the cathode of Schottky diode D102. Schottky transistors Q105 and Q106 are coupled in parallel having a common emitter that is coupled a first terminal of constant current source I101. The second terminal of constant current source I101 is coupled to ground. The collector of Schottky transistor Q105 is coupled to a first terminal of resistor R101 and the base of transistor Q101. The second terminal of resistor R101 is coupled to supply voltage V.sub.CC. Similarly, the collector of Schottky transistor Q106 is coupled to a first terminal of resistor R102 and the base of transistor Q102. Also, the second terminal of resistor R102 is coupled to supply voltage V.sub.CC.
Bandgap voltage reference V.sub.BG provides a voltage to the non-inverting input of operational amplifier OP1 that is equal to the bandgap voltage of silicon (1.25 V). Thus, the voltage V.sub.WC across resistor R.sub.WC is forced to the bandgap voltage of 1.25 V by operational amplifier OP1. The output of operational amplifier OP1 is coupled in a feedback loop through transistors Q103 and Q104 to the inverting input of operational amplifier OP1.
Voltages V.sub.DX and V.sub.DY are differential logic signals. When voltage V.sub.DX is greater than voltage V.sub.DY, transistors Q103 and Q105 are turned on, whereas, transistors Q104 and Q106 are turned off. Because transistor Q106 is off and transistor Q105 is on, the current I.sub.Q5 flowing through transistor Q105 is equal to the current through constant current source I1 and the current through transistor Q106 is zero. The voltage drop across resistor R101 due to current I.sub.Q5 turns transistor Q101 off, while the voltage at the base of transistor Q102 (approximately supply voltage V.sub.CC) turns on transistor Q102. Since transistors Q102 and Q103 are on and transistors Q101 and Q104 are off, a current (equal to V.sub.BG /R.sub.WC) is steered from the supply voltage toward ground through a conduction path comprising transistor Q102, inductive load, L.sub.HEAD, and transistor Q103.
When voltage V.sub.DX is lower than voltage V.sub.DY, transistors Q104 and Q106 are turned on, whereas, transistors Q103 and Q105 are turned off. Since transistor Q105 is off and transistor Q106 is on, the current I.sub.Q6 flowing through transistor Q106 is equal to the current through constant current source I101 and the current through transistor Q105 is zero. Thus, the voltage drop across resistor R102 due to current I.sub.Q6 turns transistor Q102 off, while the voltage at the base of transistor Q101 (approximately supply voltage V.sub.CC) turns on transistor Q101. Since transistors Q101 and Q104 are on and transistors Q102 and Q103 are off, a current (equal to V.sub.BG /R.sub.WC) is steered from the supply voltage toward ground through a conduction path comprising transistor Q101, inductive load, L.sub.HEAD, and transistor Q104.
During the write current transition, current paths are switched and the current rise time, t.sub.r, and the current fall time, t.sub.f, are given by the following equation: EQU t.sub.r =t.sub.f =L.sub.h *.DELTA.I.sub.h /V.sub.h, (1)
where L.sub.h is the head inductance, .DELTA.I.sub.h is the change in head current and V.sub.h is the head voltage swing. Equation (1) shows that the rise time and the fall time for the current transition of the write driver are inversely proportional to the head voltage swing, V.sub.h. Therefore, increasing the head voltage swing results in a faster rise and fall time for high speed magnetic recording.
Using Kirchhoff's voltage law, the voltage swing across the head mechanism, L.sub.HEAD, can be determined from FIG. 1. The write driver circuit illustrated in FIG. 1 is a symmetrical circuit having matched components, therefore the head voltage swing for the current path comprising transistors Q102-Q103 is equal to the voltage swing for the current path comprising transistors Q101-Q104. The head swing voltage is given by the following equation: EQU V.sub.h (peak)=V.sub.CC -(V.sub.BE +V.sub.WC +V.sub.CE), (2)
where V.sub.h (peak) is the peak head voltage swing, V.sub.CC is the supply voltage, V.sub.BE is the forward biased base-emitter voltage of transistors Q101-Q102, V.sub.WC is the voltage across resistor R.sub.WC, and V.sub.CE is the collector-emitter voltage of transistor Q103-Q104. Equation (2) shows that the write driver circuit of FIG. 1 only provides about 1 V peak head swing voltage at 3.3 V supply voltage operation. Thus, the prior art has the disadvantage that at 3.3 V it only provides less than half the head swing voltage of a write driver operating at 5 V.